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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Deep Power-Down
Figure 78: MRR Command to Power-Down Entry
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK#
CK
CKE 1
RL
t ISCKE
CMD
DQ
DQS#
DQS
MRR
D OUT D OUT D OUT D OUT
Note:
1. CKE can be registered LOW at (RL + RU( t DQSCK/ t CK)+ BL/2 + 1) clock cycles after the
clock on which the MRR command is registered.
Figure 79: MRW Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
t ISCKE
CKE 1
t MRW
CMD
MRW
Note:
1. CKE can be registered LOW t MRW after the clock on which the MRW command is regis-
tered.
Deep Power-Down
Deep power-down (DPD) is entered when CKE is registered LOW with CS# LOW, CA0
HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. The NOP command
must be driven in the clock cycle following power-down entry. CKE must not go LOW
while MRR or MRW operations are in progress. CKE can go LOW while other operations
such as ACTIVATE, auto precharge, PRECHARGE, or REFRESH are in progress, however,
deep power-down I DD specifications will not be applied until those operations com-
plete. The contents of the array will be lost upon entering DPD mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to
internal circuitry are disabled within the device. V REFDQ can be at any level between 0
and V DDQ , and V REFCA can be at any level between 0 and V DDCA during DPD. All power
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
101
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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